1. Field of the Invention
The present invention relates to an image processing apparatus which handles digital data in a first format (for example, an image displaying format) and a second format (for example, a medium recording format).
2. Related Background Art
An apparatus for digitally transmitting (including recording and reproducing) image data has been developed in recent years so that image transmission free of S/N degradation and recording and reproducing free of aging have been attained. The format of an image signal to be handled in such a digital image processing apparatus may include a display format (or a standard input/output format) in which pixel signals (and video sync. signals) are arranged along a direction of scan such as a monitor output or a camera input, a record format of a magnetic recording medium and a transmission/reception format in accordance with a specific transmission rule of a transmission line. Conversion between those formats is carried out as required.
In transmitting or recording an image, data is shuffled, an error correction code is added, and in each data block, a sync. code SYNC and an identification code ID are added. FIG. 1A shows a basic format in which pixel data are arranged in the order of horizontal scan and vertical scan, and FIG. 1B shows a record format of a magnetic tape in a digital VTR. The basic format shown in FIG. 1A, corresponds to the horizontal vertical scan in a video monitor.
In the digital image processing apparatus, it is common that a data memory for temporarily storing image data to be processed is equipped. In a prior art digital image processing apparatus, in order to save hardware, circuit blocks such as input/output circuit, record/reproduce circuit and data memory are coupled through a bus so that one data memory is shared. One example of such a digital image processing apparatus is a digital video tape recorder (VTR).
FIG. 2 shows a block diagram of a basic configuration of a prior art digital VTR. Numeral 10 denotes an input/output terminal to be connected to a transmission line such as a public telephone line network or a digital network, a TV camera, an image monitor or a transmission line interface unit, numeral 12 denotes an input/output circuit comprising an A/D converter, D/A converter and a predetermined interface circuit, and numeral 14 denotes a recording and reproducing circuit for digitally recording image data on a magnetic tape 16 and reproducing the signal recorded on the magnetic tape 16.
Numeral 18 denotes an encoder/decoder for encoding and decoding error correction codes of an outer code and an inner code due to the recording and reproducing, numeral 20 denotes a data memory to be used for recording and reproducing by the recording and reproducing circuit 14, for encoding and decoding the error correction code by the encoder/decoder 18 and for the input/output by the input/output circuit 12, and numeral 22 denotes a data bus for interconnecting the circuits 12, 14, 18 and 20.
A data flow through the data bus 22 is shown in FIG. 3. The writing of the data from the input/output circuit 12 to the data memory 20 is conducted in the basic format. The encoder/decoder 18 accesses the data memory 20 in the basic format (or its own format) to encode the error correction code. The recording and reproducing circuit 14 reads the data of the data memory 20 in the record format and records it on the magnetic tape 16 in sync. blocks.
In the prior art, the input/output to one data bus so frequently occurs that an access rate of the data bus and the data memory is high. Particularly when a video signal is to be processed on real time basis, a faster processing speed is required.
Where the same data memory is read and written in different formats such as the basic format and the record format, the management and control of the memory addresses are complex. In order to facilitate it, a memory address generator which is compatible to the format used should be provided in each of the circuits connected to the data bus. As a result, the circuit scale is enlarged.
In addition, in the VTR, a large amount of reproduced data may be lost by a special reproducing mode or a relatively large dust particle. In such a case, it is common to interpolate it by data of a preceding frame (or field). In the prior art configuration, however, an offset is provided, frame by frame (or field by field) in each of the write addresses and read addresses and it is switched by frame (or field) time so that the read address of the data memory does not pass the write address, as shown in FIG. 4.
As a result, even if the writing to the data memory is inhibited at the drop of the reproduced data, the data reversed in the data memory is not the data of the preceding frame but the data of the preceding preceding frame. Namely, the frame interpolation is conducted by the preceding frame data. In order to avoid it, a separate data memory for the frame interpolation should be provided. This will enlarge the circuit scale.
Further, for special reproduction in VTR such as slow reproduction or search, the access rate of the bus and the memory should be considerably raised. For example, in the slow reproduction made, the write addresses of the reproduced data to the data memory are discrete and overlapped, and until one frame (or field) of data is accumulated, it cannot be read out as a reproduced image. Thus, during that period, an image stored in another frame memory is repeatedly read.
The record data usually contains an error correction code by a multi-product code. In normal reproduction mode, since the integrity of the reproduced data is assured, a syndrome of an inner code and an outer code of the product code can be calculated on real time basis in parallel with the writing to the data memory. However, in the slow reproduction mode, since the integrity of the reproduced data is not assured, more data than the coded block should be temporarily stored in the memory and it should be serially read in the same order as that of the encoding to calculate the syndrome. Thus, in the slow reproduction mode, the access rate of the memory and the bus must be approximately 3/2 time as high as that in the normal reproduction mode even when the correction is made by only the outer code.